(VRV32A Atomic Memory Operations
p0
ccopy_reg
_reconstructor
p1
(cvp_pack
Ip
p2
c__builtin__
object
p3
Ntp4
Rp5
(dp6
Vprop_count
p7
I9
sVname
p8
g0
sVprop_list
p9
(dp10
sVip_num
p11
I9
sVwid_order
p12
I9
sVrfu_dict
p13
(dp14
sVrfu_list
p15
(lp16
(V000_AMOSWAP.W
p17
g1
(cvp_pack
Prop
p18
g3
Ntp19
Rp20
(dp21
Vitem_count
p22
I4
sg8
g17
sVtag
p23
VVP_IP009_P000
p24
sVitem_list
p25
(dp26
sg12
I0
sg15
(lp27
(V000
p28
g1
(cvp_pack
Item
p29
g3
Ntp30
Rp31
(dp32
g8
V000
p33
sg23
VVP_ISA_F009_S000_I000
p34
sVdescription
p35
Vamoswap.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2\u000aA load occurs from the address at rs1 into rd.\u000aThe value at rs2 is then written back to the address at (rs1)
p36
sVpurpose
p37
VUnprivileged ISA\u000aChapter 8.4
p38
sVverif_goals
p39
VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used
p40
sVcoverage_loc
p41
V
p42
sVpfc
p43
I3
sVtest_type
p44
I3
sVcov_method
p45
I1
sVcores
p46
I56
sVcomments
p47
g42
sVstatus
p48
g42
sVsimu_target_list
p49
(lp50
sg15
(lp51
sVrfu_list_2
p52
(lp53
sg13
(dp54
Vlock_status
p55
I0
ssbtp56
a(V001
p57
g1
(g29
g3
Ntp58
Rp59
(dp60
g8
V001
p61
sg23
VVP_ISA_F009_S000_I001
p62
sg35
Vamoswap.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2\u000aA load occurs from the address at rs1 into rd.\u000aThe value at rs2 is then written back to the address at (rs1)
p63
sg37
VUnprivileged ISA\u000aChapter 8.4
p64
sg39
VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000aZero and non-zero values of rs2 are used
p65
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp66
sg15
(lp67
sg52
(lp68
sg13
(dp69
g55
I0
ssbtp70
a(V002
p71
g1
(g29
g3
Ntp72
Rp73
(dp74
g8
V002
p75
sg23
VVP_ISA_F009_S000_I002
p76
sg35
Vamoswap.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2\u000aA load occurs from the address at rs1 into rd.\u000aThe value at rs2 is then written back to the address at (rs1)
p77
sg37
VUnprivileged ISA\u000aChapter 8.4
p78
sg39
VOutput result: \u000a\u000aAll bits of rd are toggled
p79
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp80
sg15
(lp81
sg52
(lp82
sg13
(dp83
g55
I0
ssbtp84
a(V003
p85
g1
(g29
g3
Ntp86
Rp87
(dp88
g8
V003
p89
sg23
VVP_ISA_F009_S000_I003
p90
sg35
Vamoswap.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2\u000aA load occurs from the address at rs1 into rd.\u000aThe value at rs2 is then written back to the address at (rs1)
p91
sg37
VUnprivileged ISA\u000aChapter 8.4
p92
sg39
VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception
p93
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp94
sg15
(lp95
sg52
(lp96
sg13
(dp97
g55
I0
ssbtp98
asVrfu_list_1
p99
(lp100
sg52
(lp101
sg13
(dp102
sbtp103
a(V001_AMOADD.W
p104
g1
(g18
g3
Ntp105
Rp106
(dp107
g22
I4
sg8
g104
sg23
VVP_IP009_P001
p108
sg25
(dp109
sg12
I1
sg15
(lp110
(V000
p111
g1
(g29
g3
Ntp112
Rp113
(dp114
g8
V000
p115
sg23
VVP_ISA_F009_S001_I000
p116
sg35
Vamoadd.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 + [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and added using signed arithmetic and the result iis then written back to the address at (rs1)
p117
sg37
VUnprivileged ISA\u000aChapter 8.4
p118
sg39
VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used
p119
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp120
sg15
(lp121
sg52
(lp122
sg13
(dp123
g55
I0
ssbtp124
a(V001
p125
g1
(g29
g3
Ntp126
Rp127
(dp128
g8
V001
p129
sg23
VVP_ISA_F009_S001_I001
p130
sg35
Vamoadd.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 + [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and added using signed arithmetic and the result iis then written back to the address at (rs1)
p131
sg37
VUnprivileged ISA\u000aChapter 8.4
p132
sg39
VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000a+ve, -ve and zero values of rs2 are used
p133
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp134
sg15
(lp135
sg52
(lp136
sg13
(dp137
g55
I0
ssbtp138
a(V002
p139
g1
(g29
g3
Ntp140
Rp141
(dp142
g8
V002
p143
sg23
VVP_ISA_F009_S001_I002
p144
sg35
Vamoadd.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 + [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and added using signed arithmetic and the result iis then written back to the address at (rs1)
p145
sg37
VUnprivileged ISA\u000aChapter 8.4
p146
sg39
VOutput result: \u000a\u000a+ve, -ve and zero values of rd are used\u000aAll bits of rd are toggled
p147
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp148
sg15
(lp149
sg52
(lp150
sg13
(dp151
g55
I0
ssbtp152
a(V003
p153
g1
(g29
g3
Ntp154
Rp155
(dp156
g8
V003
p157
sg23
VVP_ISA_F009_S001_I003
p158
sg35
Vamoadd.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 + [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and added using signed arithmetic and the result iis then written back to the address at (rs1)
p159
sg37
VUnprivileged ISA\u000aChapter 8.4
p160
sg39
VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception
p161
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp162
sg15
(lp163
sg52
(lp164
sg13
(dp165
g55
I0
ssbtp166
asg99
(lp167
sg52
(lp168
sg13
(dp169
sbtp170
a(V002_AMOAND.W
p171
g1
(g18
g3
Ntp172
Rp173
(dp174
g22
I4
sg8
g171
sg23
VVP_IP009_P002
p175
sg25
(dp176
sg12
I2
sg15
(lp177
(V000
p178
g1
(g29
g3
Ntp179
Rp180
(dp181
g8
V000
p182
sg23
VVP_ISA_F009_S002_I000
p183
sg35
Vamoand.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 & rs[1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ANDed and the result iis then written back to the address at (rs1)
p184
sg37
VUnprivileged ISA\u000aChapter 8.4
p185
sg39
VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used
p186
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp187
sg15
(lp188
sg52
(lp189
sg13
(dp190
g55
I0
ssbtp191
a(V001
p192
g1
(g29
g3
Ntp193
Rp194
(dp195
g8
V001
p196
sg23
VVP_ISA_F009_S002_I001
p197
sg35
Vamoand.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 & rs[1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ANDed and the result iis then written back to the address at (rs1)
p198
sg37
VUnprivileged ISA\u000aChapter 8.4
p199
sg39
VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000aZero and non-zero values of rs2 are used
p200
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp201
sg15
(lp202
sg52
(lp203
sg13
(dp204
g55
I0
ssbtp205
a(V002
p206
g1
(g29
g3
Ntp207
Rp208
(dp209
g8
V002
p210
sg23
VVP_ISA_F009_S002_I002
p211
sg35
Vamoand.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 & rs[1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ANDed and the result iis then written back to the address at (rs1)
p212
sg37
VUnprivileged ISA\u000aChapter 8.4
p213
sg39
VOutput result: \u000a\u000aAll bits of rd are toggled
p214
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp215
sg15
(lp216
sg52
(lp217
sg13
(dp218
g55
I0
ssbtp219
a(V003
p220
g1
(g29
g3
Ntp221
Rp222
(dp223
g8
V003
p224
sg23
VVP_ISA_F009_S002_I003
p225
sg35
Vamoand.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 & rs[1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ANDed and the result iis then written back to the address at (rs1)
p226
sg37
VUnprivileged ISA\u000aChapter 8.4
p227
sg39
VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception
p228
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp229
sg15
(lp230
sg52
(lp231
sg13
(dp232
g55
I0
ssbtp233
asg99
(lp234
sg52
(lp235
sg13
(dp236
sbtp237
a(V003_AMOOR.W
p238
g1
(g18
g3
Ntp239
Rp240
(dp241
g22
I4
sg8
g238
sg23
VVP_IP009_P003
p242
sg25
(dp243
sg12
I3
sg15
(lp244
(V000
p245
g1
(g29
g3
Ntp246
Rp247
(dp248
g8
V000
p249
sg23
VVP_ISA_F009_S003_I000
p250
sg35
Vamoor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 | [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ORed and the result iis then written back to the address at (rs1)
p251
sg37
VUnprivileged ISA\u000aChapter 8.4
p252
sg39
VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used
p253
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp254
sg15
(lp255
sg52
(lp256
sg13
(dp257
g55
I0
ssbtp258
a(V001
p259
g1
(g29
g3
Ntp260
Rp261
(dp262
g8
V001
p263
sg23
VVP_ISA_F009_S003_I001
p264
sg35
Vamoor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 | [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ORed and the result iis then written back to the address at (rs1)
p265
sg37
VUnprivileged ISA\u000aChapter 8.4
p266
sg39
VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000aZero and non-zero values of rs2 are used
p267
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp268
sg15
(lp269
sg52
(lp270
sg13
(dp271
g55
I0
ssbtp272
a(V002
p273
g1
(g29
g3
Ntp274
Rp275
(dp276
g8
V002
p277
sg23
VVP_ISA_F009_S003_I002
p278
sg35
Vamoor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 | [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ORed and the result iis then written back to the address at (rs1)
p279
sg37
VUnprivileged ISA\u000aChapter 8.4
p280
sg39
VOutput result: \u000a\u000aAll bits of rd are toggled
p281
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp282
sg15
(lp283
sg52
(lp284
sg13
(dp285
g55
I0
ssbtp286
a(V003
p287
g1
(g29
g3
Ntp288
Rp289
(dp290
g8
V003
p291
sg23
VVP_ISA_F009_S003_I003
p292
sg35
Vamoor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 | [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ORed and the result iis then written back to the address at (rs1)
p293
sg37
VUnprivileged ISA\u000aChapter 8.4
p294
sg39
VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception
p295
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp296
sg15
(lp297
sg52
(lp298
sg13
(dp299
g55
I0
ssbtp300
asg99
(lp301
sg52
(lp302
sg13
(dp303
sbtp304
a(V004_AMOXOR.W
p305
g1
(g18
g3
Ntp306
Rp307
(dp308
g22
I4
sg8
g305
sg23
VVP_IP009_P004
p309
sg25
(dp310
sg12
I4
sg15
(lp311
(V000
p312
g1
(g29
g3
Ntp313
Rp314
(dp315
g8
V000
p316
sg23
VVP_ISA_F009_S004_I000
p317
sg35
Vamoxor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 ^ [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise XORRed and the result iis then written back to the address at (rs1)
p318
sg37
VUnprivileged ISA\u000aChapter 8.4
p319
sg39
VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used
p320
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp321
sg15
(lp322
sg52
(lp323
sg13
(dp324
g55
I0
ssbtp325
a(V001
p326
g1
(g29
g3
Ntp327
Rp328
(dp329
g8
V001
p330
sg23
VVP_ISA_F009_S004_I001
p331
sg35
Vamoxor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 ^ [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise XORRed and the result iis then written back to the address at (rs1)
p332
sg37
VUnprivileged ISA\u000aChapter 8.4
p333
sg39
VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000aZero and non-zero values of rs2 are used
p334
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp335
sg15
(lp336
sg52
(lp337
sg13
(dp338
g55
I0
ssbtp339
a(V002
p340
g1
(g29
g3
Ntp341
Rp342
(dp343
g8
V002
p344
sg23
VVP_ISA_F009_S004_I002
p345
sg35
Vamoxor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 ^ [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise XORRed and the result iis then written back to the address at (rs1)
p346
sg37
VUnprivileged ISA\u000aChapter 8.4
p347
sg39
VOutput result: \u000a\u000aAll bits of rd are toggled
p348
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp349
sg15
(lp350
sg52
(lp351
sg13
(dp352
g55
I0
ssbtp353
a(V003
p354
g1
(g29
g3
Ntp355
Rp356
(dp357
g8
V003
p358
sg23
VVP_ISA_F009_S004_I003
p359
sg35
Vamoxor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 ^ [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise XORRed and the result iis then written back to the address at (rs1)
p360
sg37
VUnprivileged ISA\u000aChapter 8.4
p361
sg39
VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception
p362
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp363
sg15
(lp364
sg52
(lp365
sg13
(dp366
g55
I0
ssbtp367
asg99
(lp368
sg52
(lp369
sg13
(dp370
sbtp371
a(V005_AMOMAX.W
p372
g1
(g18
g3
Ntp373
Rp374
(dp375
g22
I4
sg8
g372
sg23
VVP_IP009_P005
p376
sg25
(dp377
sg12
I5
sg15
(lp378
(V000
p379
g1
(g29
g3
Ntp380
Rp381
(dp382
g8
V000
p383
sg23
VVP_ISA_F009_S005_I000
p384
sg35
Vamomax.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the largest value is then written back to the address at (rs1)
p385
sg37
VUnprivileged ISA\u000aChapter 8.4
p386
sg39
VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used
p387
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp388
sg15
(lp389
sg52
(lp390
sg13
(dp391
g55
I0
ssbtp392
a(V001
p393
g1
(g29
g3
Ntp394
Rp395
(dp396
g8
V001
p397
sg23
VVP_ISA_F009_S005_I001
p398
sg35
Vamomax.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the largest value is then written back to the address at (rs1)
p399
sg37
VUnprivileged ISA\u000aChapter 8.4
p400
sg39
VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000a+ve, -ve and zero values of rs2 are used
p401
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp402
sg15
(lp403
sg52
(lp404
sg13
(dp405
g55
I0
ssbtp406
a(V002
p407
g1
(g29
g3
Ntp408
Rp409
(dp410
g8
g407
sg23
VVP_ISA_F009_S005_I002
p411
sg35
Vamomax.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the largest value is then written back to the address at (rs1)
p412
sg37
VUnprivileged ISA\u000aChapter 8.4
p413
sg39
VOutput result: \u000a\u000a+ve, -ve and zero values of rd are used\u000aAll bits of rd are toggled
p414
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp415
sg15
(lp416
sg52
(lp417
sg13
(dp418
g55
I0
ssbtp419
a(V003
p420
g1
(g29
g3
Ntp421
Rp422
(dp423
g8
V003
p424
sg23
VVP_ISA_F009_S005_I003
p425
sg35
Vamomax.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the largest value is then written back to the address at (rs1)
p426
sg37
VUnprivileged ISA\u000aChapter 8.4
p427
sg39
VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception
p428
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp429
sg15
(lp430
sg52
(lp431
sg13
(dp432
g55
I0
ssbtp433
asg99
(lp434
sg52
(lp435
sg13
(dp436
sbtp437
a(V006_AMOMAXU.W
p438
g1
(g18
g3
Ntp439
Rp440
(dp441
g22
I4
sg8
g438
sg23
VVP_IP009_P006
p442
sg25
(dp443
sg12
I6
sg15
(lp444
(V000
p445
g1
(g29
g3
Ntp446
Rp447
(dp448
g8
V000
p449
sg23
VVP_ISA_F009_S006_I000
p450
sg35
Vamomaxu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the largest value is then written back to the address at (rs1)
p451
sg37
VUnprivileged ISA\u000aChapter 8.4
p452
sg39
VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used
p453
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp454
sg15
(lp455
sg52
(lp456
sg13
(dp457
g55
I0
ssbtp458
a(V001
p459
g1
(g29
g3
Ntp460
Rp461
(dp462
g8
V001
p463
sg23
VVP_ISA_F009_S006_I001
p464
sg35
Vamomaxu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the largest value is then written back to the address at (rs1)
p465
sg37
VUnprivileged ISA\u000aChapter 8.4
p466
sg39
VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled
p467
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp468
sg15
(lp469
sg52
(lp470
sg13
(dp471
g55
I0
ssbtp472
a(V002
p473
g1
(g29
g3
Ntp474
Rp475
(dp476
g8
V002
p477
sg23
VVP_ISA_F009_S006_I002
p478
sg35
Vamomaxu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the largest value is then written back to the address at (rs1)
p479
sg37
VUnprivileged ISA\u000aChapter 8.4
p480
sg39
VOutput result: \u000a\u000aAll bits of rd are toggled
p481
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp482
sg15
(lp483
sg52
(lp484
sg13
(dp485
g55
I0
ssbtp486
a(V003
p487
g1
(g29
g3
Ntp488
Rp489
(dp490
g8
V003
p491
sg23
VVP_ISA_F009_S006_I003
p492
sg35
Vamomaxu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the largest value is then written back to the address at (rs1)
p493
sg37
VUnprivileged ISA\u000aChapter 8.4
p494
sg39
VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception
p495
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp496
sg15
(lp497
sg52
(lp498
sg13
(dp499
g55
I0
ssbtp500
asg99
(lp501
sg52
(lp502
sg13
(dp503
sbtp504
a(V007_AMOMIN.W
p505
g1
(g18
g3
Ntp506
Rp507
(dp508
g22
I4
sg8
g505
sg23
VVP_IP009_P007
p509
sg25
(dp510
sg12
I7
sg15
(lp511
(V000
p512
g1
(g29
g3
Ntp513
Rp514
(dp515
g8
V000
p516
sg23
VVP_ISA_F009_S007_I000
p517
sg35
Vamomin.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the smaller value is then written back to the address at (rs1)
p518
sg37
VUnprivileged ISA\u000aChapter 8.4
p519
sg39
VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used
p520
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp521
sg15
(lp522
sg52
(lp523
sg13
(dp524
g55
I0
ssbtp525
a(V001
p526
g1
(g29
g3
Ntp527
Rp528
(dp529
g8
V001
p530
sg23
VVP_ISA_F009_S007_I001
p531
sg35
Vamomin.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the smaller value is then written back to the address at (rs1)
p532
sg37
VUnprivileged ISA\u000aChapter 8.4
p533
sg39
VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled
p534
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp535
sg15
(lp536
sg52
(lp537
sg13
(dp538
g55
I0
ssbtp539
a(V002
p540
g1
(g29
g3
Ntp541
Rp542
(dp543
g8
V002
p544
sg23
VVP_ISA_F009_S007_I002
p545
sg35
Vamomin.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the smaller value is then written back to the address at (rs1)
p546
sg37
VUnprivileged ISA\u000aChapter 8.4
p547
sg39
VOutput result: \u000a\u000a+ve, -ve and zero values of rd are used\u000aAll bits of rd are toggled
p548
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp549
sg15
(lp550
sg52
(lp551
sg13
(dp552
g55
I0
ssbtp553
a(V003
p554
g1
(g29
g3
Ntp555
Rp556
(dp557
g8
V003
p558
sg23
VVP_ISA_F009_S007_I003
p559
sg35
Vamomin.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the smaller value is then written back to the address at (rs1)
p560
sg37
VUnprivileged ISA\u000aChapter 8.4
p561
sg39
VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception
p562
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp563
sg15
(lp564
sg52
(lp565
sg13
(dp566
g55
I0
ssbtp567
asg99
(lp568
sg52
(lp569
sg13
(dp570
sbtp571
a(V008_AMOMINU.W
p572
g1
(g18
g3
Ntp573
Rp574
(dp575
g22
I4
sg8
g572
sg23
VVP_IP009_P008
p576
sg25
(dp577
sg12
I8
sg15
(lp578
(V000
p579
g1
(g29
g3
Ntp580
Rp581
(dp582
g8
V000
p583
sg23
VVP_ISA_F009_S008_I000
p584
sg35
Vamominu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the smaller value is then written back to the address at (rs1)
p585
sg37
VUnprivileged ISA\u000aChapter 8.4
p586
sg39
VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used
p587
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp588
sg15
(lp589
sg52
(lp590
sg13
(dp591
g55
I0
ssbtp592
a(V001
p593
g1
(g29
g3
Ntp594
Rp595
(dp596
g8
V001
p597
sg23
VVP_ISA_F009_S008_I001
p598
sg35
Vamominu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the smaller value is then written back to the address at (rs1)
p599
sg37
VUnprivileged ISA\u000aChapter 8.4
p600
sg39
VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled
p601
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp602
sg15
(lp603
sg52
(lp604
sg13
(dp605
g55
I0
ssbtp606
a(V002
p607
g1
(g29
g3
Ntp608
Rp609
(dp610
g8
V002
p611
sg23
VVP_ISA_F009_S008_I002
p612
sg35
Vamominu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the smaller value is then written back to the address at (rs1)
p613
sg37
VUnprivileged ISA\u000aChapter 8.4
p614
sg39
VOutput result: \u000a\u000aAll bits of rd are toggled
p615
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp616
sg15
(lp617
sg52
(lp618
sg13
(dp619
g55
I0
ssbtp620
a(V003
p621
g1
(g29
g3
Ntp622
Rp623
(dp624
g8
V003
p625
sg23
VVP_ISA_F009_S008_I003
p626
sg35
Vamominu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the smaller value is then written back to the address at (rs1)
p627
sg37
VUnprivileged ISA\u000aChapter 8.4
p628
sg39
VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception
p629
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp630
sg15
(lp631
sg52
(lp632
sg13
(dp633
g55
I0
ssbtp634
asg99
(lp635
sg52
(lp636
sg13
(dp637
sbtp638
asVrfu_list_0
p639
(lp640
sg99
(lp641
sVvptool_gitrev
p642
V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $
p643
sVio_fmt_gitrev
p644
V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $
p645
sVconfig_gitrev
p646
V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
p647
sVymlcfg_gitrev
p648
V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
p649
sbtp650
.